Coding "HALFADDER" using VHDL code

Library ieee;

Use ieee.std_logic_1164.all;

Entity halfadd is

Port (A, B : in std_logic;

Sum, Cout: out std_logic);

End halfadd;

Architecture myadd of halfadd is

Begin

Sum <= A xor B;

Cout <= A and B;

End myadd;