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Saturday, September 24, 2011

Coding "HALFADDER" using VHDL code

Library ieee;
Use ieee.std_logic_1164.all;

Entity halfadd is
Port (A, B : in std_logic;
Sum, Cout: out std_logic);
End halfadd;

Architecture myadd of halfadd is
Begin
Sum <= A xor B;
Cout <= A and B;
End myadd;

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